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    • 专利摘要:
    The invention relates to a method of manufacturing an optoelectronic device (10), comprising the following successive steps: a) providing a substrate at least partly made of a semiconductor material and having opposite first and second faces; b) forming light-emitting diodes (16) on the substrate, each light-emitting diode comprising a semiconductor microfil or semiconductor nanowire (46); c) forming an encapsulation layer (50) surrounding the light emitting diodes; d) forming conductive pads (18) on the encapsulation layer, on the side of the encapsulation layer opposite to the substrate, in contact with the light-emitting diodes; and e) forming through apertures (26) in the substrate from the side of the second face, said apertures facing at least in part the light-emitting diodes and defining walls (28) in the substrate.
    公开号:FR3061608A1
    申请号:FR1663508
    申请日:2016-12-29
    公开日:2018-07-06
    发明作者:Zheng-Sung Chio；Wei Sin Tan；Vincent Beix；Philippe Gilet
    申请人:Aledia；
    IPC主号:
    专利说明:

    Holder (s):
    Applicant (s): ALEDIA Simplified joint stock company - FR.
    Inventor (s): CHIO ZHENG-SUNG, TAN WEI SIN, BEIX VINCENT and GILET PHILIPPE.
    ALEDIA Simplified joint-stock company.
    ® Agent (s): CABINET BEAUMONT.
    (54) OPTOELECTRONIC DEVICE WITH LIGHT EMITTING DIODES.
    FR 3,061,608 - A1 (57) The invention relates to a method for manufacturing an optoelectronic device (10), comprising the following successive steps:
    a) providing a substrate at least partially made of a semiconductor material and having first and second opposite faces;
    b) forming light emitting diodes (16) on the substrate, each light emitting diode comprising a semiconductor microfil or nanowire (46) covered with a shell;
    c) forming an encapsulation layer (50) surrounding the light emitting diodes;
    d) forming conductive pads (18) on the encapsulation layer, on the side of the encapsulation layer opposite the substrate, in contact with the light-emitting diodes; and
    e) forming through openings (26) in the substrate from the side of the second face, said openings facing at least in part the light emitting diodes and delimiting walls (28) in the substrate.

    B15657 - Backside NW
    OPTOELECTRONIC DEVICE WITH LIGHT EMITTING DIODES
    Field
    The present application relates to an optoelectronic device, in particular a display screen or an image projection device, with light-emitting diodes based on semiconductor materials and their manufacturing methods. Presentation of the prior art
    One pixel of an image corresponds to the unitary element of the image displayed by the optoelectronic device. When the optoelectronic device is a screen for displaying color images, it generally comprises, for the display of each pixel of the image, at least three components, also called display subpixels, which each emit light radiation substantially in only one color (for example, red, green and blue). The superposition of the radiations emitted by these three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the display pixel of the optoelectronic device is the assembly formed by the three display sub-pixels used for displaying a pixel of an image.
    There are optoelectronic devices comprising light emitting diodes having semiconductor elements of micrometric or nanometric size, for example
    B15657 - Backside NW example in at least one element of group III and one element of group V, hereinafter called compound III-V, in particular gallium nitride (GaN).
    Optoelectronic devices can include blocks of photoluminescent materials formed on the light emitting diodes. Each block is adapted to convert the radiation emitted by the light-emitting diodes into desired radiation. The blocks are located on the light emitting diodes according to the arrangement of the sub-pixels.
    In an image display device, crosstalk occurs when the light emitted by the light emitting diode associated with a sub-pixel reaches the photoluminescent block associated with another sub-pixel. In order to reduce the crosstalk between sub-pixels and increase the contrast, it is known to provide opaque or reflective walls between the photoluminescent blocks. Walls can be formed by electroplating techniques. However, these techniques do not generally make it possible to form walls having an aspect ratio which is adapted to the dimensions of the sub-pixels and photoluminescent blocks, in particular for sub-pixels having a lateral dimension of less than 15 μm. It is desirable to have tall, thin walls. Standard technologies make it possible to form either a high and thick wall or a thin and small wall. In particular, it is desirable to obtain an aspect ratio as high as possible, and preferably greater than 5. It is further desirable to reduce the space occupied by the walls.
    There are methods of making optoelectronic devices which include forming trenches in a substrate to delimit the sub-pixels. However, it is difficult to have a high density of trenches to obtain a fine pitch, in particular for sub-pixels having a lateral dimension of less than 15 μm.
    There are also methods of making optoelectronic devices which include removing all or part of the substrate on which the light emitting diodes
    B15657 - Backside NW are formed. However, there may be a risk of cracking when removing the substrate and forming the walls.
    summary
    Thus, an object of an embodiment is to at least partially overcome the drawbacks of the optoelectronic devices described above comprising light-emitting diodes having micrometric or nanometric semiconductor elements, arranged to form display subpixels.
    A other object of a fashion of production East than the crosstalk between adjacent sub-pixels is reduced. A other object of a fashion of production East than the contrast East increases. A other object of a fashion of production East than the
    optoelectronic device comprises sub-pixels having a lateral dimension less than 15 µm.
    Thus, one embodiment provides a method of manufacturing an optoelectronic device comprising the following successive steps:
    a) providing a substrate at least partially made of a semiconductor material and having first and second opposite faces;
    b) forming light-emitting diodes on the substrate, each light-emitting diode comprising a semiconductor microfil or nanowire covered with a shell;
    c) forming an encapsulation layer surrounding the light-emitting diodes;
    d) forming conductive pads on the encapsulation layer, on the side of the encapsulation layer opposite the substrate, in contact with the light-emitting diodes; and
    e) forming through openings in the substrate from the side of the second face, said openings facing at least partially light-emitting diodes and delimiting walls in the substrate.
    B15657 - Backside NW
    According to one embodiment, the method further comprises the step of:
    f) forming photoluminescent blocks in at least some of the openings.
    According to one embodiment, step b) comprises the formation of a germination layer in contact with the substrate, the germination layer being made of a material promoting the growth of the semiconductor microfil or nanowire and growing the wires on the layer germination.
    According to one embodiment, the germination layer may be at least partly made of aluminum nitride, boron, boron nitride, titanium, titanium nitride, tantalum, tantalum nitride, hafnium, hafnium nitride, niobium, niobium nitride, zirconium, zirconium borate, zirconium nitride, silicon carbide, tantalum nitride and carbide, magnesium nitride in the form Mg x Ny, where x is equal to 3 to 10% and y is equal to 2 to 10%, in magnesium and gallium nitride, in tungsten, in tungsten nitride, or in a combination of these compounds.
    According to one embodiment, the method further comprises, before step e), the step of thinning the substrate.
    According to one embodiment, the method further comprises, before step e), the step of fixing the encapsulation layer to an electronic circuit or to a handle.
    According to one embodiment, the method further comprises, before step d), the step of etching trenches in the encapsulation layer between the light-emitting diodes and the step of covering each trench with an insulating coating. electrically, and at least partial filling of each trench with a filling material and / or the maintenance of air or a partial vacuum in each trench.
    According to one embodiment, in step d), the conductive pads are formed in contact with the shells.
    According to one embodiment, the method comprises, before step d), the step of etching portions of the shells to expose
    B15657 - Backside NW the ends of the semiconductor microwires or nanowires, the conductive pads, in step d) being formed in contact with the semiconductor microfibers or nanowires and being electrically isolated from the shells.
    According to one embodiment, each semiconductor microfil or nanowire comprises lateral faces and a crown face opposite to the substrate and in which, for each light-emitting diode, the shell covers the lateral faces and the crown face of the microfil or nanowire.
    According to one embodiment, each microfil or nanowire of the lateral faces and a semiconductor comprises opposite the electroluminescent substrate, the microfil or nanowire.
    and in which, for shell covers only the face of each vertex face vertex diode
    Another embodiment provides optoelectronics comprising:
    light emitting diodes, a device each light emitting diode comprising a semiconductor microfil or nanowire covered with an electroluminescent being shell, surrounded by a diode encapsulation layer;
    walls at least in one on the semiconductor resting walls delimiting openings, in part encapsulation layer, said openings facing material said at least in part with light-emitting diodes; and conductive pads, on the side of the encapsulation layer opposite the walls, in contact with the light-emitting diodes.
    According to one embodiment, the device further comprises photoluminescent blocks in at least some of the openings.
    According to one embodiment, the device further comprises, between the walls and the encapsulation layer, a germination layer in contact with the walls, the germination layer
    B15657 - Backside NW being made of a material favoring the growth of semiconductor microfibers or nanowires.
    According to one embodiment, the germination layer may be at least partly made of aluminum nitride, boron, boron nitride, titanium, titanium nitride, tantalum, tantalum nitride, hafnium, hafnium nitride, niobium, niobium nitride, zirconium, zirconium borate, zirconium nitride, silicon carbide, tantalum nitride and carbide, magnesium nitride in the form Mg x Ny, where x is equal to 3 to 10% and y is equal to 2 to 10%, in magnesium and gallium nitride, in tungsten, in tungsten nitride, or in a combination of these compounds.
    According to one embodiment, the device further comprises trenches extending in the encapsulation layer, each trench being at least covered with a reflective coating.
    According to one embodiment, the conductive pads are in contact with the shells.
    According to one embodiment, the conductive pads are in contact with the semiconductor microwires or nanowires and are electrically isolated from the shells.
    Brief description of the drawings
    These objects, characteristics and advantages, as well as others will be described in detail in the following description of particular embodiments made without implied limitation in relation to the attached figures among which:
    Figures 1 and 2 are schematic sectional views of an embodiment of an optoelectronic device;
    Figure 3 is a more detailed sectional view of a light emitting diode of the optoelectronic device of Figure 1;
    Figures 4 and 5 are views similar to Figures 1 and 3 respectively of another embodiment of an optoelectronic device;
    B15657 - Backside NW FIGS. 6A to 6F are sectional views, partial and diagrammatic, of structures obtained in successive stages of an embodiment of a method of manufacturing the optoelectronic device shown in FIGS. 1 and 2;
    FIGS. 7A to 7F are sectional views, partial and schematic, of structures obtained at successive stages of an embodiment of a method for manufacturing the optoelectronic device shown in FIG. 4; and Figures 8 to 12 are sectional views, partial and schematic, of embodiments of optoelectronic devices.
    detailed description
    For the sake of clarity, the same elements have been designated by the same references in the different figures and, moreover, as is usual in the representation of electronic circuits, the various figures are not drawn to scale. In addition, only the elements useful for understanding this description have been shown and are described. In particular, the means for biasing a light-emitting diode of an optoelectronic device are well known to those skilled in the art and are not described.
    In the following description, unless indicated otherwise, the terms substantially, approximately and in the order of mean to within 10%. In addition, the active area of a light emitting diode is the region of the light emitting diode from which most of the electromagnetic radiation supplied by the light emitting diode is emitted. In addition, when a first element is said to be connected to a second element by an epitaxy relation, this means that the first element is formed from a first layer and that the second element is formed from a second layer which is formed by epitaxy on the first layer or vice versa.
    In addition, the term particle as used in the context of the present application must be understood in a broad sense
    B15657 - Backside NW and corresponds not only to compact particles having more or less a spherical shape but also to angular particles, flattened particles, particles in the form of flakes, particles in the form of fibers, or fibrous particles, etc. . It will be understood that the particle size in the context of the present application means the smallest transverse dimension of the particles. By particles of a material is meant the particles taken individually, that is to say the unitary elements of the material, knowing that the material can be in the form of agglomerates of particles. The expression “average particle size” is understood to mean, according to the present application, the arithmetic mean of the sizes of the particles, that is to say the sum of the sizes of the particles divided by the number of particles. The particle size can be measured by laser particle size using, for example, a Malvern Mastersizer 2000.
    The present application relates to optoelectronic devices comprising light-emitting diodes comprising semiconductor elements of micrometric or nanometric size, in particular semiconductor microwires or nanowires.
    The term microfil · or nanowire designates a three-dimensional structure of elongated shape in a preferred direction of which at least two dimensions, called minor dimensions, are between 5 nm and 2.5 pm, preferably between 50 nm and 2.5 pm, the third dimension, called major dimension, being greater than or equal to 1 time, preferably greater than or equal to 5 times and even more preferably greater than or equal to 10 times, the largest of the minor dimensions. In certain embodiments, the minor dimensions may be less than or equal to approximately 1 μm, preferably between 100 nm and 1 μm, more preferably between 100 nm and 800 nm. In certain embodiments, the height of each microfil or nanowire can be greater than or equal to 500 nm, preferably between 1 μm and 50 μm.
    B15657 - Backside NW
    In the following description, the term yarn is used to mean microfil or nanowire. Preferably, the mean line of the wire which passes through the barycenters of the straight sections, in planes perpendicular to the preferred direction of the wire, is substantially rectilinear and is hereinafter called the axis of the wire. The base of the wire has, for example, a cross section having a hexagonal, circular or square shape depending on the crystal structure of the wire.
    In the description which follows, embodiments will be described in the case of an optoelectronic device with light-emitting diodes comprising semiconductor elements in the form of microfils or nanowires with a constant cross section. However, in all of these embodiments, the elements in the form of microfibers or nanowires can be replaced by elements having the form of microfibers or nanowires with a cross section which varies, for example microfibers or nanowires having the form of a cone or trunk of cone.
    Figures 1 and 2 show an embodiment of an optoelectronic device 10, for example corresponding to a display screen or to an image projection device. Figure 3 is a more detailed view of part of Figure 1.
    The device 10 comprises two integrated circuits 12, 14. The first integrated circuit 12 comprises light-emitting diodes 16 and is called an optoelectronic circuit or optoelectronic chip in the following description. The second integrated circuit 14 comprises electronic components, not shown, in particular transistors, used for controlling the light-emitting diodes 16 of the first integrated circuit 12. The second integrated circuit 14 is called the control circuit or control chip in the rest of the description. The optoelectronic circuit 12 is fixed to the control circuit 14. Depending on the type of fixing, fixing pads 18 may be present between the optoelectronic chip 12 and the control chip 14.
    B15657 - Backside NW
    The optoelectronic circuit 12 comprises from bottom to top in FIG. 1:
    a semiconductor substrate 20 comprising a lower face 22 and an upper face 24, the upper face 24 preferably being plane at least at the level of the light-emitting diodes 16;
    openings 26 extending into the substrate 20 from the lower face 22 to the upper face 24, the parts of the substrate 20 between adjacent openings 26 forming first walls 28;
    a coating reflecting or absorbing light or a waveguide 30 covering the lateral faces of each opening 26;
    an electrically conductive layer 32 covering the coverings 30, the bottom of each opening 26 and further covering the underside 22 at least between the openings 26;
    photoluminescent blocks 34 located in at least some of the openings 26, the other openings possibly being filled with a transparent material or filled with air;
    filters 36 on the underside 22 covering at least some of the photoluminescent blocks 34;
    a germination layer 38 of a material favoring the growth of the wires and disposed on the upper face 24 on the walls 28, the germination layer 38 comprising through openings 40 for each photoluminescent block 34;
    an insulating layer 42 covering the germination layer 38 and the photoluminescent blocks 34 and comprising openings 44;
    wires 46, each wire 46 being in contact with the conductive layer 32 through one of the openings 44;
    for each wire, a shell 48, shown only in FIG. 3, comprising a stack of semiconductor layers covering the wire 46, the assembly formed by each wire 46 and the associated shell 48 forming the light-emitting diode 16, the
    B15657 - Backside NW hull 48 further comprising an active area, not shown, which is the layer from which the majority of the electromagnetic radiation supplied by the light-emitting diode 16 is emitted;
    an electrically insulating encapsulation layer 50 covering the insulating layer 42, extending around the light-emitting diodes 16 and delimiting an upper face 52;
    second reflecting walls 54 extending through the encapsulation layer 50 and surrounding each light-emitting diode 16; and an electrically conductive element 56, called via in
    the description who follows, extending through of the layer encapsulation 50 and in contact with the substrate 20 of side of the face 24. In figure 1, it is shown only a wire 46
    associated with each opening 26. According to another embodiment, two wires 46 or more than two wires 46 can be associated with the same opening 26, each wire 46 associated with the same opening 26 being in contact with the conductive layer 32 at the bottom of said opening 26.
    As shown in FIG. 2, in the present embodiment, the walls 54 form a grid and the light-emitting diodes 16 are arranged in rows and columns. By way of example, nine sub-pixels Pix are shown in FIG. 2. The walls 28 can be aligned with the walls 54 and also form a grid. In the present embodiment, the openings 26 may have a square shape. However, the shape of the openings 26 may be different. According to another embodiment, each opening 26 can have a hexagonal shape, for example centered on the light-emitting diode 16.
    The fixing pads 18 are located on the face 52 and are in contact with the light-emitting diodes 16. According to one embodiment, a fixing pad 18 is provided for each sub-pixel Pix. A fixing stud 58 is arranged on the face 52 in contact with the via conductor 56.
    B15657 - Backside NW
    In operation, voltages are applied between the pads 18 and the pad 58 so that, for each sub-pixel Pix, the light-emitting diode 16 of the sub-pixel Pix emits light with an intensity which depends on the voltage applied between the pad 58 and the fixing pad 18 associated with the sub-pixel Pix. The walls 28 and 54 reduce the crosstalk between adjacent Pix sub-pixels. Crosstalk includes the wavelengths of visible light (such as blue light emitted by the light emitting diode) and invisible light (such as ultraviolet emitted by the light emitting diode), and the light intensity (brightness). In Figure 1, only one pad 58 and only one via 56 are shown. According to one embodiment, several studs 58 and several vias 56 can be provided.
    The wires 46 are at least partly made of at least one semiconductor material. The semiconductor material can be silicon, germanium, silicon carbide, a III-V compound, a II-VI compound, or a combination of at least two of these compounds.
    The wires 46 can be, at least in part, made of semiconductor materials mainly comprising a III-V compound, for example a III-N compound. Examples of group III elements include gallium (Ga), indium (In) or aluminum (Al). Examples of III-N compounds are GaN, AIN, InN, InGaN, AlGaN or AlInGaN. Other elements of group V can also be used, for example, phosphorus or arsenic. Generally, the elements in compound III-V can be combined with different molar fractions.
    The wires 46 may be, at least in part, made of semiconductor materials mainly comprising a compound II-VI. Examples of group II elements include group IIA elements, including beryllium (Be) and magnesium (Mg) and group IIB elements, including zinc (Zn), cadmium (Cd) and mercury ( Hg). Examples of elements from group VI include elements from group VIA, including oxygen (O) and tellurium (Te). Examples of compounds II-VI
    B15657 - Backside NW are ZnO, ZnMgO, CdZnO, CdZnMgO, CdHgTe, CdTe or HgTe. Generally, the elements in compound II-VI can be combined with different molar fractions.
    The wires 46 may include a dopant. For example, for III-V compounds, the dopant can be chosen from the group comprising a P type dopant from group II, for example, magnesium (Mg), zinc (Zn), cadmium (Cd ) or mercury (Hg), a group IV type P dopant, for example carbon (C) or a group IV type N dopant, for example silicon (Si), germanium (Ge), selenium (Se), sulfur (S), terbium (Tb) or tin (Sn).
    The height of each wire 46 can be in the range of 250 nm to 50 µm. Each wire 46 can have a semiconductor structure elongated along an axis substantially perpendicular to the face 24. Each wire 46 can have a hexagonal cross section. The axes of two adjacent wires 46 can be distant from 0.3 μm to 10 μm and preferably from 1 μm to 5 μm. By way of example, the wires 46 can be distributed evenly, in particular according to a hexagonal network.
    In FIG. 3, the shell 48 covers the lateral faces and the top face of the wire 46. According to one embodiment, the shell 48 may be present only on the top face of the wire 46 opposite the substrate 20.
    The shell 48 may comprise a stack of several layers comprising in particular:
    - An active area at least partially covering the wire 46;
    - An intermediate layer of conductivity type opposite to the wire 46 and covering the active layer; and
    - a bonding layer covering the intermediate layer and in contact with the pad 18.
    The active area is the layer from which most of the radiation supplied by the light emitting diode LED is emitted. According to one example, the active area may include means of confinement. The active area can include a quantum well
    B15657 - Single NW backside. It can then comprise a semiconductor material different from the semiconductor material forming the wires 46 and the intermediate layer and having a band gap less than that of the wires 46. The active zone can comprise multiple quantum wells. It then comprises a stack of semiconductor layers forming an alternation of quantum wells and barrier layers. It is for example formed by an alternation of layers of GaN and InGaN, such a stack being generally called a heterostructure. The GaN and InGaN layers can have respective thicknesses of 3 nm to 20 nm (for example 6 nm) and from 1 nm to 10 nm (for example 2.5 nm). The GaN layers can be doped, for example, of N or P type. According to another example, the active layer can comprise a single layer of InGaN, having for example a thickness greater than 10 nm. Preferably, the layers of the active area are connected to the wire 46 by an epitaxy relationship.
    The intermediate layer, for example P-type doped, can correspond to a semiconductor layer or to a stack of semiconductor layers and allows the formation of a PN or PIN junction, the active layer being between the P-type intermediate layer and the wire 46 of the PN or PIN junction.
    The bonding layer can correspond to a semiconductor layer or to a stack of semiconductor layers and allows the formation of an ohmic contact between the intermediate layer and the pad 18. For example, the bonding layer can be very strongly doped. of the type opposite to the lower portion of the wire 46, to degenerate the semiconductor layers, for example doped P-type at a concentration greater than or equal to 10 ^ 0 atoms / cm ^.
    The stack of semiconductor layers may comprise an electron blocking layer of a ternary alloy, for example of gallium and aluminum nitride (AlGaN) or of indium and aluminum nitride (AlInN) in contact with the active layer and the intermediate layer, to ensure good distribution of the electrical carriers in the active layer.
    B15657 - Backside NW
    The substrate 20 is at least partly made of at least one semiconductor material. The semiconductor material can be silicon, germanium, silicon carbide, a III-V compound, a II-VI compound, or a combination of at least two of these compounds. Preferably, the substrate 20 is made of a semiconductor material compatible with the manufacturing methods implemented in microelectronics. The substrate 20 can be heavily doped, lightly doped or undoped. Preferably, the substrate 20 is made of monocrystalline silicon.
    The height of the walls 28, measured in a direction perpendicular to the face 24, is in the range of 1 µm to 200 µm, preferably 5 µm to 30 µm. The thickness of the walls 28, measured in a direction parallel to the face 24, is in the range of 100 nm to 50 pm, preferably from 1 pm to 10 pm. In the view of FIG. 2, the area of a sub-pixel Pix delimited by the walls 54 corresponds to the area of a square whose side varies from 0.1 pm to 100 pm, preferably from 1 pm at 30 pm.
    The germination layer 38 is made of a material promoting the growth of the wires 46. The germination layer 38 can correspond to a multilayer structure. By way of example, the material making up the germination layer 38 can be a nitride, a carbide or a boride of a transition metal from column IV, V or VI of the periodic table of the elements or a combination of these compounds. By way of example, the germination layer 38 can be made of aluminum nitride (AIN), boron (B), boron nitride (BN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride (NbN), zirconium (Zr), zirconium borate (ZrB2), zirconium nitride (ZrN), silicon carbide (Sic), nitride and tantalum carbide (TaCN), or magnesium nitride in the form Mg x Ny, where x is approximately equal to 3 and y is approximately equal to 2, for example magnesium nitride in the form Mg3N2 or magnesium and gallium nitride (MgGaN), in tungsten (W), in tungsten nitride (WN), or in a combination of these
    B15657 - Backside NW compounds. The germination layer 38 can be doped with the same type of conductivity as the substrate 20. The height of the germination layer 38, measured in a direction perpendicular to the face 24, is in the range of 10 nm to 10 μm, preferably between 20 nm and 100 nm. Preferably, the wires 46 are connected to the germination layer 38 by an epitaxy relationship. According to one embodiment, the germination layer 38 may not be, for example, a metal copper (Cu), gold (Pd), zinc (Zn) such as gold-tin (CuAg), conductive material, by (Al ), silver (Ag), nickel (Ni), palladium present.
    The pads 18, 58 are in such a form 1 'aluminum (Au), tin (Sn), the alloy or alloys of two and three of these metals (AuSn), silver-tin (AgSn), copper-silver nickel -palladium (NiPd).
    The openings 26 can be filled with the photoluminescent blocks 34. According to one embodiment, all the openings 26 are filled with the photoluminescent blocks 34. According to another embodiment, certain photoluminescent openings 26 are filled with the open blocks 26 photoluminescent openings 26 and some
    born are not filled with the blocks 34. According to an embodiment, all the born are not filled with the blocks 34. Each block photoluminescent 34 includes
    photoluminescent of suitable phosphors, when excited by the light emitted by the light emitting diode emit light at a wavelength of light emitting light 16.
    of the sub-pixel emitted wave by the
    Pix, diode
    Each photoluminescent block 34 comprises particles of at least one photoluminescent material. An example of a photoluminescent material is the yttrium aluminum garnet (YAG) activated by the cerium ion trivais, also called YAG: Ce or YAG: Ce3 +. The average particle size of conventional photoluminescent materials is generally greater than 5 µm.
    B15657 - Backside NW
    According to one embodiment, each photoluminescent block 34 comprises a matrix in which are dispersed nanocrystalline particles of nanometric size of a semiconductor material, also called semiconductor nanocrystals or nanoluminophor particles thereafter. The internal quantum yield QYi nt of a photoluminescent material is equal to the ratio between the number of photons emitted and the number of photons absorbed by the photoluminescent substance. The internal quantum yield QYi n t of the semiconductor nanocrystals is greater than 5%, preferably greater than 10%, more preferably greater than 20%.
    According to one embodiment, the average size of the nanocrystals is in the range of 0.5 nm and 1000 nm, preferably from 0.5 nm to 500 nm, even more preferably from 1 nm to 100 nm, in particular from 2 nm to 30 nm. For dimensions less than 50 nm, the photoconversion properties of semiconductor nanocrystals essentially depend on quantum confinement phenomena. The semiconductor nanocrystals then correspond to quantum dots.
    According to one embodiment, the semiconductor material of the semiconductor nanocrystals is chosen from the group comprising cadmium selenide (CdSe), indium phosphide (InP), cadmium sulfide (CdS), zinc sulfide (ZnS) , zinc selenide (ZnSe), cadmium telluride (CdTe), zinc telluride (ZnTe), cadmium oxide (CdO), zinc and cadmium oxide (ZnCdO), zinc sulfide and cadmium (CdZnS), zinc and cadmium selenide (CdZnSe), silver and indium sulfide (AgInS2) and a mixture of at least two of these compounds. According to one embodiment, the semiconductor material of the semiconductor nanocrystals is chosen from the materials cited in the publication in the name of Le Blevenec et al. de Physica Status Solidi (RRL) - Rapid Research Letters Volume 8, No. 4, pages 349-352, April 2014.
    According to one embodiment, the dimensions of the semiconductor nanocrystals are chosen according to the length
    B15657 - NW backside of wanted wave of radiation emitted by semiconductor nanocrystals. For example, CdSe nanocrystals with an average size of around 3.6 nm are suitable for converting blue light to red light and CdSe nanocrystals with an average size of around 1.3 nm are suitable for converting blue light to green light. According to another embodiment, the composition of the semiconductor nanocrystals is chosen according to the desired wavelength of the radiation emitted by the semiconductor nanocrystals.
    The matrix is made of an at least partially transparent material. The matrix is, for example, made of silica. The matrix is, for example, made of any polymer that is at least partially transparent, in particular silicone, epoxy or polyacetic acid (PLA). The matrix may be made of an at least partially transparent polymer used with three-dimensional printers, such as PLA. According to one embodiment, the matrix contains from 2% to 90%, preferably from 10% to 60%, by weight of nanocrystals, for example about 20% by weight of nanocrystals.
    The thickness of the photoluminescent blocks 34 depends on the concentration of nanocrystals and on the type of nanocrystals used. The height of the photoluminescent blocks 34 is preferably less than the sum of the height of the walls 28 and of the germination layer 38.
    The insulating layer 42 can be made of a dielectric material, for example silicon oxide (SiC ^), silicon nitride (Si x Ny, where x is approximately equal to 3 and y is approximately equal to 4, for example S13N4 ), in silicon oxynitride (in particular of general formula SiO x Ny, for example of SigO ^), in hafnium oxide (HfC ^) or in diamond. The thickness of the insulating layer 42, measured in a direction perpendicular to the face 24, is in the range of 0.01 µm to 5 µm, preferably 0.05 µm to 0.5 µm. The insulating layer 42 may correspond to a monolayer structure or to a multilayer structure of different dielectric materials from the previous list.
    B15657 - Backside NW
    The conductive layer 32 is adapted to polarize each wire 46 and to allow the electromagnetic radiation emitted by the light-emitting diodes LED to pass. The conductive layer 32 can be made of a conductive and transparent material such as graphene or a transparent conductive oxide (TCO), for example indium tin oxide (ITO) or zinc oxide doped with aluminum ( AZO) or gallium-doped zinc oxide (GZO). By way of example, the conductive layer 32 has a thickness in the range of 5 nm to 1000 nm, preferably from 20 nm to 100 nm.
    The coatings 30 can correspond to reflective coatings, for example of a metal such as aluminum, silver, copper, ruthenium or zinc. The coatings 30 can also correspond to waveguides, for example in one or multiple dielectric materials. The coatings 30 may correspond to coatings absorbing light (for example comprising a dark colored surface) by ensuring good contrast with respect to the neighboring sub-pixels when the sub-pixel is off. Each coating 30 may correspond to the combination of a reflective coating and a waveguide or a light absorbing coating and a waveguide.
    The walls 54 and via 56 can be of a metal such as aluminum, silver, copper or zinc. The walls 54 may include a core covered with a reflective layer, for example of a metal such as aluminum, silver, copper or zinc. The heart can be made of a dielectric material. According to one embodiment, the hearts of the walls 54 correspond to cavities which can be filled with air or a partial vacuum. The height of the walls 54 is preferably approximately the same as the height of the wires 46. The thickness of the walls 54, measured in a direction parallel to the face 24, is in the range of 100 nm to 50 µm, preferably 500 nm to 10 pm. The minimum distance between the walls 54 and the shells 48 is in the range of 1 µm to 50 µm, preferably 3 µm to 10 µm.
    B15657 - Backside NW
    The encapsulation layer 50 is made of one or more dielectric materials, for example the materials described for the insulating layer 42. According to one embodiment, the encapsulation layer 50 comprises, for each light-emitting diode 16, a first layer surrounding said light emitting diode 16 and a second layer surrounding the first layer. The first and second layers may be made of dielectric materials, for example the materials described for the insulating layer 42.
    Figures 4 and 5 are sectional views, partial and schematic, similar to Figures 1 and 3 respectively of another embodiment of an optoelectronic device 60 comprising light emitting diodes. The optoelectronic device 60 comprises the same elements as the optoelectronic device 10 shown in FIGS. 1 and 3 with the difference that the conductive layer 32 is not present, that it comprises an electrically conductive layer 62 covering part of each shell 48 and in contact with the walls 54 and with via 56 and that the studs 18 are in electrical contact with the wires 46 and are insulated from the shells 48 by an electrically insulating layer 64.
    The electrically conductive layer 62 can be of the same material as layer 32. The thickness of the conductive layer 62 is in the range of 5 nm to 1000 nm, preferably 20 to 200 nm.
    The insulating layer 64 can be of the same material as the insulating layer 50. The thickness of the insulating layer 64 is in the range from 10 nm to 1000 nm, preferably from 50 nm to 300 nm.
    FIGS. 6A to 6F are partial and schematic sectional views of the structures obtained at successive stages of an embodiment of a method for manufacturing the optoelectronic device 10 shown in FIGS. 1 to 3.
    FIG. 6A represents the structure obtained after the following steps:
    B15657 - Backside NW provide a monobloc substrate 70 having two opposite faces 72, 74;
    forming the germination layer 38 on the face 74 of the substrate 70;
    forming the insulating layer 42 on the germination layer 38;
    forming the openings 44 in the insulating layer 42; and forming the light-emitting diodes 16 on the germination layer 38, that is to say forming the wires 46 on the germination layer 38 and forming the shells 48, not shown in FIG. 6A, on the wires 46.
    The substrate 70 is of the same material as the substrate 20. The germination layer 38 can be produced by a process such as chemical vapor deposition (CVD) or chemical vapor deposition with organometallics (MOCVD), also known by the name organometallic vapor phase epitaxy (MOVPE). However, processes such as molecular beam epitaxy (MBE), gas source MBE (GSMBE), organometallic MBE (MOMBE), plasma assisted MBE (PAMBE), atomic layer epitaxy (ALE ), hydride vapor epitaxy (HVPE) can be used, as well as atomic layer deposition (ALD). In addition, methods such as evaporation or sputtering can be used.
    The wires 46 and the shells 48 can be formed by a method of the CVD, MOCVD, MBE, GSMBE, PAMBE, ALE, HVPE, ALD type. An example of a process for manufacturing wires 46 and shells is described in patent application US2015 / 0280053. For each light-emitting diode 16, the shell 48 can cover the lateral faces and the top face of the wire 46. According to another embodiment, the shell 48 may be present only on the top face of the wire 46 opposite the substrate 70.
    FIG. 6B represents the structure obtained after the following steps:
    B15657 - Backside NW etching the insulating layer 42 and the germination layer 38 at least at the location where the via 56 is to be formed;
    forming an encapsulation layer 78 on the insulating layer 42 and on the wire 16, the height of the encapsulation layer 78 being greater than the height of the light-emitting diode 16; and forming openings or trenches 80 through the encapsulation layer 50 at the locations where the walls 54 and via 56 are to be formed. The dimensions of the openings 80 correspond to the desired dimensions of the walls 54 and of the via 56. The etching is stopped on the insulating layer 42 or the germination layer 38 for the openings 80 provided for the walls 54. The etching is stopped on the substrate 70 for the opening 80 provided for via 56. The etching implemented can be a dry etching, in particular when vertical walls are required for the walls 54, for example by using a plasma based on chlorine or fluorine or an etching reactive ion (RIE).
    FIG. 6C represents the structure obtained after the following steps : form a layer conductive on the layer encapsulation 50, layer conductive filling them out openings 80;engrave the layer conductive and the layer encapsulation 78 to the tops of the hulls 48 of diodes electroluminescent 16, from which it results the formation of the layer
    encapsulation 50, walls 54 and via 56.
    FIG. 6D represents the structure obtained after the following steps:
    forming the pads 18, 58 on the encapsulation layer 50 and in contact with the shells 48 of the light-emitting diodes 16, the pads 18 being in contact with the shells 48 of the light-emitting diodes 16 and the pad 58 is in contact with the via 56 ;
    B15657 - Backside NW attach a support 84, also called a handle, to the encapsulation layer 50, using a bonding material 85; and thin the substrate 70 from the side opposite the support 84 to form the substrate 20.
    The pads 18 and 58 may preferably be formed by electrochemical deposition of an electrically conductive layer on the encapsulation layer 50, the conductive layer being formed of the material of the contact pads 18 and 58, and by etching the conductive layer to delimit the contact pads 18 and 58. The etching implemented can be a dry etching, for example using a plasma based on chlorine and fluorine, a reactive ion etching (RIE) or a wet etching (for example using l hydrofluoric acid HF).
    FIG. 6E represents the structure obtained after the following steps:
    etching the openings 26 in the substrate 20 and in the germination layer 38 up to the insulating layer 42 to expose the base of each wire 46;
    forming the reflective coating 30 on the lateral faces of each opening 26; and form the conductive layer 32.
    The dimensions of the openings 26 correspond to the desired dimensions of the photoluminescent blocks 34. This etching can be stopped on the insulating layer 42. The etching used can be a dry etching, for example using a plasma based on chlorine and fluorine, a Reactive ion etching (RIE) or a wet etching preferably an anisotropic wet etching using potassium hydroxide (KOH) for Si <100> and <111>.
    FIG. 6F represents the structure obtained after the following steps:
    forming the photoluminescent blocks 34 in the openings 26;
    B15657 - Backside NW etch the parts of the photoluminescent blocks 34 outside the openings 26; and form the filters 36.
    The photoluminescent blocks 34 can be formed by filling certain openings 26 with a colloidal dispersion of semiconductor nanocrystals in a bonding matrix, for example by a so-called additive process, possibly by sealing certain openings 26 with resin. The so-called additive process can include direct printing of the colloidal dispersion at the desired locations, for example by ink jet printing, aerosol printing, micro-buffering, photoengraving, screen printing, flexography, spray coating, or drop deposition.
    By removing the handle 84 and the connecting material 85, the optoelectronic chip 12 shown in FIG. 1 is obtained.
    In the present embodiment, the attachment of the control chip 14 to the optoelectronic chip 12 can be carried out using inserts such as connection microbeads or studs of boss type 18. As a variant, the attachment of the control chip 14 to the optoelectronic chip 12 can be produced by direct bonding, without the use of inserts. Direct bonding may include direct metal-to-metal bonding of metal areas of the optoelectronic chip 12 and metal areas of the control chip 14 and dielectric-dielectric bonding of dielectric areas to the surface of the optoelectronic chip 12 and dielectric areas on the surface of the control chip 14. The attachment of the control chip 14 to the optoelectronic chip 12 can be carried out by a thermocompression process in which the optoelectronic chip 12 is pressed against the control chip 14, with application of pressure and heating.
    FIGS. 7A to 7F are partial and schematic sectional views of the structures obtained at successive stages of an embodiment of a method for manufacturing the optoelectronic device 60 represented in FIG. 4.
    B15657 - Backside NW
    Figure ΊΆ shows the structure obtained after the steps described above in relation to Figure 6Ά and after the step of forming the conductive layer 62 covering the insulating layer 42 and covering the shells 48 of the light emitting diodes 16 with the exception of the tops of shells 48. According to one embodiment, at this stage, the conductive layer 62 completely covers the shells 48.
    FIG. 7B represents the structure obtained after the steps described above in relation to FIGS. 6B and 6C with the difference that the encapsulation layer 50 is formed on the conductive layer 62 and that the conductive layer 62 is not etched on the surface. location of via 56. The encapsulation layer 50 is arranged between the wires 46 and / or the walls 54 and the via 56.
    FIG. 7C represents the structure obtained after the following steps:
    engrave the tops of the shells 48 to expose the ends of the wires 46;
    forming the electrically insulating layer 64 covering the encapsulation layer 50; and etching openings 86 in the insulating layer 64 to expose the ends of the wires 46 and to expose the via 56.
    The lateral dimension of an opening 86 is less than the lateral dimension of the wire 46. According to an example, when the lateral dimension of the wire 46 is approximately 0.5 μm, the lateral dimension of an opening 86 may be of about 0.3 pm.
    FIG. 7D represents the structure obtained after the steps described above in relation to FIG. 6D, the studs 18 being in contact with the ends of the wires 46.
    FIG. 7E represents the structure obtained after the following steps:
    etch the openings 26 in the substrate 20, the germination layer 38 and the insulating layer 42 to expose the conductive layer 62 and the wires 46 and the shells 48.
    FIG. 7F represents the structure obtained after the following steps:
    B15657 - Backside NW form the reflective coating 30 on the lateral faces of each opening 26; and the steps described above in relation to FIG. 6F.
    After removal of the handle 84, the optoelectronic chip 12 shown in FIG. 4 is obtained.
    Figures 8 to 12 show different variants of the optoelectronic device 60 shown in Figure 4. In these figures, the control chip 14 is not shown.
    Figure 8 is a sectional, partial and schematic view, similar to Figure 4 of another embodiment of an optoelectronic device 90 comprising light emitting diodes. The optoelectronic device 90 comprises the same elements as the optoelectronic device 60 shown in FIG. 4, and further comprises the conductive layer 32 shown in FIG. 1, the conductive layer 32 being in contact with the conductive layer 62. However, the conductive layer 32 is etched around each light-emitting diode 16 so as to prevent the conductive layer 32 from being in contact with the wires 46. An increase in the electrical and thermal conductivity is obtained.
    Figure 9 is a sectional, partial and schematic view, similar to Figure 8 of another embodiment of an optoelectronic device 95 comprising light emitting diodes. The optoelectronic device 95 comprises the same elements as the optoelectronic device 90 shown in FIG. 8 with the difference that the walls 54 are not in contact with the conductive layer 62. The method of manufacturing the optoelectronic device 95 can be simpler than the method for manufacturing the optoelectronic device 90 since, in the step shown in FIG. 7B in which the openings 80 are etched, the etching process does not have to be selected to stop on the conductive layer 62.
    B15657 - Backside NW
    Figure 10 is a sectional, partial and schematic view, similar to Figure 8 of another embodiment of an optoelectronic device 100 comprising light emitting diodes. The optoelectronic device 100 comprises the same elements as the optoelectronic device 90 shown in FIG. 8 with the difference that certain studs 18 are connected together. Preferably, the pads 18 connected together are associated with adjacent sub-pixels emitting the same color. Therefore, for two light-emitting diodes 16 associated with the pads 18 connected, if one of the light-emitting diodes does not work, there may always be an emission of light by the other light-emitting diode. In addition, for two light-emitting diodes or wires 16 associated with the pads 18 connected, if one of the pads 18 is not correctly connected to the control circuit 14, there is always a connection between the control circuit 14 and the circuit optoelectronics 12 by the other pad 18.
    Figure 11 is a sectional, partial and schematic view, similar to Figure 8 of another embodiment of an optoelectronic device 105 comprising light emitting diodes. The optoelectronic device 105 comprises the same elements as the optoelectronic device 90 shown in FIG. 8 with the difference that the germination layer 38 is not etched in the openings 26. The method of manufacturing the optoelectronic device 105 can be simpler than the manufacturing process of the optoelectronic device 90 since there is no etching of the germination layer 38.
    Figure 12 is a sectional, partial and schematic view, similar to Figure 8 of another embodiment of an optoelectronic device 110 comprising light emitting diodes. The optoelectronic device 110 comprises the same elements as the optoelectronic device 90 shown in FIG. 8 with the difference that the reflective coatings 30 are not present. The manufacturing process
    B15657 - Backside NW of the optoelectronic device 110 can be simpler than the manufacturing process of the optoelectronic device 90.
    Particular embodiments have been described. Various variants and modifications will appear to those skilled in the art. In particular, although in the embodiments described above the optoelectronic chip 12 is fixed directly to the control chip 14, the optoelectronic chip 12 and the control chip 14 can each be fixed to a printed circuit. Furthermore, although in the embodiments described above, the walls 28 and 54 have lateral faces which are substantially perpendicular to the face 24, the lateral faces of the walls 28 and 54 can be profiled, for example being inclined relative to the face 24.
    Furthermore, although in the embodiments described above, the substrate 70 is a one-piece substrate, the substrate 70 may correspond to a multilayer structure, for example an SOI structure comprising an insulating layer covering a semiconductor base and a semiconductor layer covering the layer insulating. In the steps described above in relation to FIGS. 6D and 7D in which the substrate 70 is thinned, the semiconductor base and the insulating layer covering the semiconductor base can be removed to leave the semiconductor layer which corresponds to the substrate 20.
    In addition, various embodiments with various variants have been described above. Various elements of these embodiments and variants can be combined. By way of example, the modifications applied to the optoelectronic device 60 and shown in FIGS. 9 to 12 can be applied to the optoelectronic device 10 shown in FIG. 1.
    B15657 - Backside NW
    权利要求:
    Claims (18)
    [1" id="c-fr-0001]
    1. Method for manufacturing an optoelectronic device (10; 60; 90; 95; 100; 105; 110) comprising the following successive steps:
    a) providing a substrate (70) at least partly made of a semiconductor material and having first and second opposite faces (72, 74);
    b) forming light-emitting diodes (16) on the substrate, each light-emitting diode comprising a semiconductor microfil or nanowire (46) covered with a shell (48);
    c) forming an encapsulation layer (50) surrounding the light emitting diodes;
    d) forming conductive pads (18) on the encapsulation layer, on the side of the encapsulation layer opposite the substrate, in contact with the light-emitting diodes; and
    e) forming through openings (26) in the substrate from the side of the second face (72), said openings facing at least partially the light emitting diodes and delimiting walls (28) in the substrate.
    [2" id="c-fr-0002]
    2. Method according to claim 1, further comprising the step of:
    f) forming photoluminescent blocks (34) in at least some of the openings.
    [3" id="c-fr-0003]
    3. Method according to claim 1 or 2, wherein step b) comprises the formation of a germination layer (38) in contact with the substrate (70), the germination layer being made of a material promoting the growth of semiconductor microfil or nanowire (46) and grow the wires (46) on the germination layer.
    [4" id="c-fr-0004]
    4. Method according to claim 3, in which the germination layer (38) may be at least partly made of aluminum nitride (AIN), boron (B), boron nitride (BN), titanium (Ti) ), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride ( NbN), in zirconium (Zr), in
    B15657 - Backside NW zirconium borate (ZrBg), zirconium nitride (ZrN), silicon carbide (Sic), nitride and tantalum carbide (TaCN), magnesium nitride in the form Mg x Ny, where x is equal to 3 to 10% and is equal to 2 to 10%, in magnesium and gallium nitride (MgGaN), in tungsten (W), in tungsten nitride (WN), or in a combination of these compounds.
    [5" id="c-fr-0005]
    5. Method according to any one of claims 1 to 4, further comprising, before step e), the step of thinning the substrate (70).
    [6" id="c-fr-0006]
    6. Method according to any one of claims 1 to 5, further comprising, before step e), the step of fixing the encapsulation layer (50) to an electronic circuit (14) or to a handle (84).
    [7" id="c-fr-0007]
    7. Method according to any one of claims 1 to 6, further comprising, before step d), the step of etching trenches (80) in the encapsulation layer (50) between the light-emitting diodes (16 ) and the step of covering each trench with an electrically insulating coating (54), and filling at least partially each trench with a filling material and / or maintaining air or a partial vacuum in each trench.
    [8" id="c-fr-0008]
    8. Method according to any one of claims 1 to 7, wherein, in step d), the conductive pads (18) are formed in contact with the shells (48).
    [9" id="c-fr-0009]
    9. Method according to any one of claims 1 to 7, comprising, before step d), the step of etching portions of the shells (48) to expose the ends of the semiconductor microfibers or nanowires (46), the pads conductors (18), in step d) being formed in contact with the semiconductor microwires or nanowires and being electrically isolated from the shells.
    [10" id="c-fr-0010]
    10. The method as claimed in any one of claims 1 to 9, in which each semiconductor microfil or nanowire (46) comprises lateral faces and a crown face opposite the substrate (70) and in which, for each diode
    B15657 - Electroluminescent NW backside (16), the shell (48) covers the lateral faces and the top face of the microfil or nanowire.
    [11" id="c-fr-0011]
    11. Method according to any one of claims 1 to 9, in which each semiconductor microfil or nanowire (46) comprises lateral faces and an apex face opposite the substrate (70) and in which, for each light-emitting diode (16) , the shell (48) covers only the top face of the microfil or nanowire.
    [12" id="c-fr-0012]
    12. Optoelectronic device (10; 60; 90; 95; 100; 105; 110) comprising:
    light emitting diodes (16), each light emitting diode comprising a semiconductor microfil or nanowire (46) covered with a shell (48), the light emitting diodes being surrounded by an encapsulation layer (50);
    walls (28) at least in part made of a semiconductor material resting on the encapsulation layer, said walls delimiting openings (26), said openings (26) facing at least partly light-emitting diodes; and conductive pads (18), on the side of the encapsulation layer opposite the walls, in contact with the light-emitting diodes.
    [13" id="c-fr-0013]
    13. Device according to claim 12, further comprising photoluminescent blocks (34) in at least some of the openings (26).
    [14" id="c-fr-0014]
    14. Device according to claim 12 or 13, further comprising, between the walls (28) and the encapsulation layer (50), a germination layer (38) in contact with the walls, the germination layer being in one material that promotes the growth of semiconductor microfibers or nanowires (46).
    [15" id="c-fr-0015]
    15. Device according to claim 14, in which the germination layer (38) can be at least partly made of aluminum nitride (AIN), boron (B), boron nitride (BN), titanium
    B15657 - Backside NW (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb) , niobium nitride (NbN), zirconium (Zr), zirconium borate (ZrB2), zirconium nitride (ZrN), silicon carbide (SiC), nitride and tantalum carbide (TaCN), magnesium nitride in the form Mg x Ny, where x is equal to 3 to 10% and y is equal to 2 to 10%, in magnesium and gallium nitride (MgGaN), in tungsten (W), in nitride tungsten (WN), or a combination of these compounds.
    [16" id="c-fr-0016]
    16. Device according to any one of claims 12 to 15, further comprising trenches (80) extending in the encapsulation layer (50), each trench being at least covered with a reflective coating (54).
    [17" id="c-fr-0017]
    17. Device according to any one of claims 12 to 16, wherein the conductive pads (18) are in contact with the shells (48).
    [18" id="c-fr-0018]
    18. Device according to any one of claims 12 to 16, in which the conductive pads (18) are in contact with the semiconductor microwires or nanowires (46) and are electrically isolated from the shells (48).
    B 15657
    1/6
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    法律状态:
    2017-12-21| PLFP| Fee payment|Year of fee payment: 2 |
    2018-07-06| PLSC| Search report ready|Effective date: 20180706 |
    2019-12-17| PLFP| Fee payment|Year of fee payment: 4 |
    2020-12-29| PLFP| Fee payment|Year of fee payment: 5 |
    优先权:
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    FR1663508|2016-12-29|FR1663508A| FR3061608B1|2016-12-29|2016-12-29|OPTOELECTRONIC DEVICE WITH LIGHT EMITTING DIODES|
    PCT/EP2017/084778| WO2018122355A1|2016-12-29|2017-12-28|Optoelectronic device with light-emitting diodes|
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    CN201780086474.4A| CN110313069A|2016-12-29|2017-12-28|Optoelectronic device with light emitting diode|
    TW106146178A| TWI758392B|2016-12-29|2017-12-28|Optoelectronic device with light-emitting diodes and method for manufacturing the same|
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